The invention relates to phase detector circuits and methods. More particularly, the invention relates to digital phase detector circuits and methods having optional lock window offset and lock window extension features.
Phase detector circuits are commonly used in today""s digital integrated circuits. For example, a phase detector circuit is included in virtually every phase lock loop (PLL) and delay lock loop (DLL). A phase detector circuit is a circuit that compares the corresponding edges (e.g., rising edges) of two input clock signals, and provides two output signals indicating the phase relationship between the two input clock signals. The two output signals (sometimes called xe2x80x9cUpxe2x80x9d and xe2x80x9cDownxe2x80x9d, or xe2x80x9cAddxe2x80x9d and xe2x80x9cSubtractxe2x80x9d) indicate whether a feedback clock signal needs to be delayed or moved forward in order to be in phase with a reference clock signal. Some phase detector circuits also supply a third output signal (e.g., xe2x80x9cLockxe2x80x9d) that indicates when the two input clock signals are in phase and no adjustment is needed.
FIG. 1 is a block diagram of an exemplary system that includes a phase detector circuit. System 100 includes a clock adjust circuit 101 (e.g., a DLL in the pictured embodiment), a clock network 102, circuit elements 103, and phase detector circuit 104. Clock adjust circuit 101 includes a finite state machine 112, a delay chain including delay elements D0-Dn, and a multiplexer 111. The input clock signal CLKIN is provided to state machine 112, to the first element D0 in the delay chain, and to multiplexer 111. State machine 112 controls multiplexer 111 via select signal SEL to select one of the delayed clock signals from the delay chain. Thus, the amount of delay through clock adjust circuit 101 from input terminal CLKIN to output terminal CLKOUT depends on the state of state machine 112, which in turn depends on the signals ADD and SUB from phase detector 104.
Output signal CLKOUT from clock adjust circuit 101 is provided to a clock network 102, which drives the various circuit elements 103 included in the system. Clock network 102 also provides feedback clock signal FBCLK to phase detector circuit 104. Phase detector circuit 104 compares the phase of feedback clock signal FBCLK to the phase of input clock signal CLKIN, providing signals ADD and SUB. Signals ADD and SUB, in turn, control state machine 112 to either add more delay or shorten the delay through clock adjust circuit 101, as necessary to align corresponding edges of the two clock signals FBCLK and CLKIN. Phase detector circuit 104 is clocked by input clock signal CLKIN, and can optionally be reset by signal RST, which can also be used to reset state machine 112.
Optional output signal LOCK from phase detector circuit 104 can be used for various purposes, e.g., to enable and disable additional circuitry. For example, a system can include two clock adjust circuits coupled in series. The first clock adjust circuit can perform a coarse phase adjustment, and the second clock adjust circuit can perform a fine phase adjustment. The LOCK signal from the first clock adjust circuit can be used to enable the second clock adjust circuit only after a coarse lock has been achieved.
FIGS. 2-4 illustrate three value combinations for signals LOCK, ADD, and SUB. In FIG. 2, input clock signal CLKIN and feedback clock signal FBCLK are in phase. In this example, being xe2x80x9cin phasexe2x80x9d means the rising edges of the two clocks occur at the same time. Thus, the relative phase of the two signals is xe2x80x9clockedxe2x80x9d, and the delay through the clock adjust circuit need not be changed. Signal LOCK is high (1), and signals ADD and SUB are low (0).
In FIG. 3, the rising edge of the feedback clock precedes the rising edge of the input clock by a time xe2x88x92Delta. Thus, additional delay needs to be added to the path through the clock delay circuit to bring the feedback clock signal FBCLK into phase with the input clock signal CLKIN. Thus, signal LOCK is low, signal ADD is high, and signal SUB is low. Because the clock signals are periodic signals, the clocks could also be brought into phase by reducing the delay through the clock delay circuit. However, it is preferable to make the smallest adjustment that will have the desired effect.
In FIG. 4, the rising edge of the feedback clock follows the rising edge of the input clock by a time +Delta. Thus, some of the delay needs to be removed from the path through the clock delay circuit to bring the feedback clock signal FBCLK into phase with the input clock signal CLKIN. Thus, signal LOCK is low, signal ADD is low, and signal SUB is high. Because the clock signals are periodic signals, the clocks could also be brought into phase by increasing the delay through the clock delay circuit. However, as noted above, it is preferable to make the smallest adjustment that will have the desired effect.
Returning now to FIG. 1, in the ideal case clock adjust circuit 101 operates as follows. When reset signal RST is high, signal SEL selects the clock input signal CLKIN as output clock signal CLKOUT. When reset signal RST goes low, signal ADD goes high. Clock adjust circuit 101 continues inserting additional delay into the clock path between the CLKIN and CLKOUT terminals until feedback clock signal FBCLK is precisely in phase with input clock signal CLKIN. At that point, signal LOCK goes high and signal ADD goes low. State machine 112 holds the current selection in multiplexer 111. However, if variations occur in temperature, power high voltage level, or the frequency of input clock signal CLKIN, the two edges can lose synchronization. In this case, one of signals ADD and SUB goes high, and signal LOCK goes low. Finite state machine 112 selects a differently delayed clock signal to provide to the CLKOUT terminal of clock adjust circuit 101, until the feedback clock signal FBCLK is again in phase with the input clock signal CLKIN. At that point, signal LOCK again goes high, while signals ADD and SUB are both low.
The previous paragraph describes the behavior of the clock adjust circuit in the ideal case. However, in the ideal case the delay through the clock adjust circuit has infinitely small gradations and the two clock signals can be precisely synchronized. Thus, exactly one of signals LOCK, ADD, and SUB can be high at any given time. However, in reality, it is often true that the two clock signals are rarely precisely synchronized. Nevertheless, the LOCK signal must be allowed to signal a lock on the clock signal. Therefore, a xe2x80x9clock windowxe2x80x9d, is frequently provided, wherein the LOCK signal is active (e.g., high) whenever the feedback clock edge occurs within a predetermined time of the input clock edge. Hence, the LOCK signal can be high at the same time as one or the other of the ADD and SUB signals.
FIG. 5 illustrates the concept of a lock window. The lock window ranges from a time xe2x88x92Delta_syn preceding the input clock edge to a time +Delta_syn following the input clock edge. Whenever the corresponding edge (e.g., the rising edge) of the feedback clock signal FBCLK falls within this window, signal LOCK is high.
A small lock window is desirable when high accuracy is required. However, a small lock window makes the phase detector circuit sensitive to clock jitter. Therefore, some known systems include phase detector circuits having programmable lock windows. For example, one known DLL has a lock window that supports two predetermined values of Delta_syn. When the DLL first becomes active, Delta_syn has a first and lower value. Thus, the clock signals are precisely locked. However, as soon as the two clock signals are locked (e.g., signal LOCK goes high), the lock window is extended by increasing the value of Delta_syn. This feature reduces noise and power consumption by causing the DLL to go inactive again until the new extended window is exceeded.
Clearly, phase detector circuits are common and useful circuits. Therefore, it is desirable to provide improved phase detector circuits, e.g., phase detector circuits having glitch-free output signals. Further, it is desirable to provide flexible phase detector circuits that can be adapted for use in a variety of systems and applications.
The invention provides simple, glitch-free phase detector circuits that provide add and subtract output signals indicating the phase relationship between two input clock signals. Some embodiments also provide a lock output signal having a lock window, and in some of these embodiments, the size of the lock window is programmable with respect to the feedback clock. An optionally delayed version of the feedback clock signal is stored a first time when the input clock signal goes high, then stored a second time after a predetermined delay. In some embodiments, the predetermined delay is programmable. When both stored values are low, the subtract output signal is active. When the first stored value is high, the add output signal is active, regardless of the state of the second stored value. When the first stored value is low and the second stored value is high, the two clocks are synchronized and the phase detector indicates a lock condition.
According to one embodiment, a phase detector circuit includes a feedback input terminal, a clock input terminal, subtract and add output terminals, first and second memory elements, a first delay element, and a first logic gate. The first memory element has a clock terminal coupled to the clock input terminal of the phase detector circuit, a data input terminal coupled to the feedback input terminal of the phase detector circuit, and an output terminal coupled to the add output terminal of the phase detector circuit. The second memory element has a clock terminal, a data input terminal coupled to the feedback input terminal of the phase detector circuit, and an output terminal. The first delay element is coupled between the clock input terminal of the phase detector circuit and the clock terminal of the second memory element. The first logic gate has a first input terminal coupled to the output terminal of the first memory element, a second input terminal coupled to the output terminal of the second memory element, and an output terminal coupled to the subtract output terminal of the phase detector circuit. Finally, a signal on the add output terminal of the phase detector circuit is independent of a signal on the output terminal of the second memory element.
According to another embodiment, a system includes a clock input terminal, a clock adjust circuit, a clock network, a plurality of circuit elements, and a phase detector circuit. The clock adjust circuit has a clock input terminal coupled to the clock input terminal of the system, a subtract input terminal, an add input terminal, and a clock output terminal. The clock network has an input terminal coupled to the clock output terminal of the clock adjust circuit, a feedback output terminal, and additional output terminals. The circuit elements have clock input terminals coupled to the additional output terminals of the clock network.
The phase detector circuit includes a feedback input terminal, a clock input terminal, subtract and add output terminals, first and second memory elements, a first delay element, and a first logic gate. The feedback input terminal is coupled to the feedback output terminal of the clock network. The clock input terminal is coupled to the clock input terminal of the system. The subtract output terminal is coupled to the subtract input terminal of the clock adjust circuit. The add output terminal is coupled to the add input terminal of the clock adjust circuit. The first memory element has a clock terminal coupled to the clock input terminal of the phase detector circuit, a data input terminal coupled to the feedback input terminal of the phase detector circuit, and an output terminal coupled to the add output terminal of the phase detector circuit. The second memory element has a clock terminal, a data input terminal coupled to the feedback input terminal of the phase detector circuit, and an output terminal. The first delay element is coupled between the clock input terminal of the phase detector circuit and the clock terminal of the second memory element. The first logic gate has a first input terminal coupled to the output terminal of the first memory element, a second input terminal coupled to the output terminal of the second memory element, and an output terminal coupled to the subtract output terminal of the phase detector circuit. Finally, a signal on the add output terminal of the phase detector circuit is independent of a signal on the output terminal of the second memory element.
Another embodiment provides a method of detecting and reporting a difference in phase between an input clock signal and a feedback clock signal. The method includes: storing a first value of the feedback clock signal in a first memory element when the input clock signal changes state in a predetermined direction; delaying the input clock signal to provide a delayed input clock signal; storing a second value of the feedback clock signal in a second memory element when the delayed input clock signal changes state in the predetermined direction; providing an active subtract signal when each of the first and second memory elements stores a first predetermined value; and providing an active add signal when the first memory element stores a second predetermined value.